The evolution of lightwave technology follows in significant respects the development of silicon technology, in which the first devices were discrete components. Later came silicon device hybrid integration of a few devices on a substrate, followed by full integration of millions of devices on a small chip. The development of lightwave technology is progressing through the discrete component phase, in which lasers and photodetectors are packaged individually and coupled together with fiber pigtails, and in which passive devices like couplers and multiplexers are implemented using lengths of optical fiber. For the growth of this technology to continue on a learning curve comparable to silicon technology it is necessary to move to the next level, i.e. fully hybrid lightwave ICs. Although the integration of multiple optical components on a single substrate has been proposed in many forms, the successful migration of this technology to full hybridization requires the development of a reliable standard platform for integrating multiple lightwave components and subassemblies. There is a need for effective means for integrating monolithic arrays of active devices, as well as combinations of active and passive devices.
A strong candidate for this standard platform in future lightwave systems is silicon optical bench technology. The use of silicon as the basic substrate has several attractive aspects. Among these is the v-groove technology that was developed two decades ago for optical fiber couplers. In optical bench technology, the coupling of light between components of the hybrid lightwave circuit, as well as the coupling light at the input and output terminations of the circuit, can be implemented with great precision, and with passive alignment, using v-groove technology. Another attribute of silicon optical bench technology is that it uses the sophisticated silicon processing and processing equipment that has already been developed for silicon integrated circuits.
Among the techniques that optical bench technology has borrowed from silicon IC processing is the batch processing of integrated circuits on large silicon wafers. After fabrication of the integrated circuits, the wafers are affixed to tape carriers, then diced into discrete chips using diamond saws or laser scribing tools. The separated chips are then bonded to lead frames or ceramic substrates and packaged in e.g. a dual-in-line (DIP) package.
In the standard silicon wafer fabrication technique debris from the dicing operation is typically cleaned using a standard cleaning process. Much of the debris is removed using flowing water in the dicing apparatus, and that which remains in general does not create troublesome residue deposits and staining because the surface of the wafer is typically passivated, with the exception of small bonding pad areas.
In the manufacture of optical integrated circuits residual debris from the standard dicing operation has been found to be more troublesome. Residue deposits and staining of the integrated circuit surface are often so severe that the resulting product fails customer acceptance. This problem is attributed in part to the fact that the silicon wafers used in optical bench technology are thicker than those used in silicon IC fabrication. Thus the dicing operation typically produces more debris. In addition, major features of the surface of the optical integrated circuit are typically exposed during dicing, in contrast to the passivated surface of silicon ICs. An unclean surface at this stage in the process will interfere with wire bonding, soldering, positioning, and other attachment operations performed in later stages of fabrication. The surface of optical integrated circuits may comprise several materials, e.g. silicon, gold, platinum, titanium, that are more susceptible to staining than the deposited silicon oxide that is present at this stage in silicon IC processing. Moreover, the feature size in optical ICs is typically large, making stains that occur more visible.
These residues and stains in optical bench technology are not acceptable. Thus the need arises for a different approach to debris removal in the wafer dicing operation.
Cleaning operations at the chip level are either carried out by removing the chips from a tape carrier and mass cleaning in a cleaning solution either unrestricted or, to avoid damage to the chips, mounted in a special package. After cleaning, the chips are remounted on a tape carrier and inserted into the chip bonder, or are retained in the cleaning package for chip bonding. In either case, substantial handling of the individual chips is required.
It is much preferable to conduct the dicing debris clean-up at the wafer level. Mild cleaning operations can be implemented after dicing while the chips remain bonded to the tape carrier. However, we have found that mild cleansers are not adequate in solving the staining problem just outlined. The use of more aggressive cleaning agents, e.g. the strong acidic or basic solutions used in typical silicon IC fabrication, have been found effective in removing the stains, however they attack the adhesive on the tape carrier. Thus this approach leaves the process designer with the option earlier mentioned, with attendant cost and inconvenience, of performing the cleaning operation at the chip level.
Thus there is a need in optical bench technology for a process that successfully overcomes the staining problem after wafer dicing, and does not add a cleaning operation at the chip level.